Computer Engineering · University of Florida

I build systems from signals to software.

Computer Engineering student working across digital hardware, embedded systems, systems software, and machine learning. I care most about the boundaries between them—where firmware meets networks, processors shape software, and models meet real constraints.

View selected work erikwoods17@gmail.com

Seeking Summer 2027 engineering internships

One project, end to end ESP32 telemetry path

01 / INPUT DHT22 temperature + humidity

02 / EDGE ESP32 C++ firmware + Wi-Fi

03 / SYSTEM Flask + SQLite API + persistence

04 / OUTPUT Dashboard live browser view

01 / Selected work

Projects are the evidence.

A curated set of systems that show the problem, implementation, and technical decisions—not just a list of tools.

Hardware & Architecture Embedded · Networking · Backend

ESP32 Wi-Fi Weather Station

Making sensor data useful beyond the serial monitor.

ESP32 firmware samples a DHT22, computes environmental readings and device diagnostics, then sends structured telemetry over Wi-Fi to a Flask API. SQLite persists each reading and the browser dashboard presents current conditions, trends, connection failures, and sensor freshness.

Edge: C++ firmware sends temperature, humidity, RSSI, and uptime in JSON without fabricating a board-voltage reading.
Service: Separate Flask routes receive telemetry, query history, and serve the latest reading.
Interface: Reading age now drives explicit LIVE, STALE, and OFFLINE states, while backend failures surface separately.

ESP32 · C++ · DHT22 · Wi-Fi · Flask · SQLite · JavaScript

View repository

ESP32 weather station dashboard showing temperature, humidity, Wi-Fi signal, uptime, and device status — Live telemetry dashboard · actual project interface

Hardware & Architecture SystemVerilog · RISC-V

Single-Cycle RV32I Processor

Building a CPU small enough to explain and rigorous enough to verify end to end.

An educational 32-bit single-cycle processor implementing a seven-instruction RV32I subset: ADD, SUB, ADDI, LW, SW, BEQ, and JAL. The RTL separates decode, immediate generation, register-file access, ALU execution, memory, writeback, and next-PC control. It is intentionally a verified subset rather than a claim of full RV32I compliance.

Datapath: Combinational decode, register reads, ALU, data reads, writeback, and next-PC selection feed sequential state updates on the rising edge.
Control: Unsupported encodings and invalid word accesses suppress state writes and freeze the PC instead of silently producing undefined behavior.
Verification: Independent Python encoders support self-checking unit and integration tests in Icarus Verilog, with instruction traces and VCD waveforms.

SystemVerilog · RISC-V RV32I · Icarus Verilog · Python · Make

View repository

Single-cycle datapath verified RV32I subset

01 / FETCH PC + instruction 32-bit byte-addressed flow

02 / CONTROL Decode 7 supported RV32I operations

03 / EXECUTE ALU + branch arithmetic · address · equality

04 / STATE Memory + WB data memory · register file

Hardware & VerificationSystemVerilog

FIFO + UART TX

A parameterized single-clock FIFO and independent 8-N-1 UART transmitter, each backed by self-checking SystemVerilog testbenches. The FIFO covers ordering, wraparound, simultaneous operations, overflow and underflow; the UART verifies framing, busy behavior, reset, and multiple clocks-per-bit settings.

SystemVerilog · RTL · Icarus Verilog · randomized regression · VCD

View repository

VERIFICATION PATH / REPRODUCIBLE

01Directed casesreset · fill/drain · framing

02Seeded regressionFIFO + UART stimulus

03Reference checksqueue model · symbol timing

04WaveformsVCD inspection when needed

Edge AI & Embedded MLQuantized inference

Edge AI Sensor Classifier

A six-class activity classifier built from UCI HAR inertial windows using 12 compact statistical features. A softmax linear model is exported to int8 weights and int32 accumulation for standalone C++ inference, with an ESP32 replay sketch for exported test vectors. Live sensing and on-board execution are not claimed.

Python · C++17 · int8 quantization · ESP32 sketch · UCI HAR

View repository

Held-out test accuracy · 2,947 windows

Majority baseline

18.22%

Float model

77.37%

Quantized model

77.30%

Float/quantized prediction agreement: 98.00%. Host results only; ESP32 latency remains unmeasured.

CATCHUP / GROUP CHAT CURRENT PROJECT

TODAY

AminaLibrary at 3:30? I booked the room upstairs.

Jordanyeah, bringing the lab notes

ErikI’ll be there after digital logic.

Systems & Software Current project

CatchUp

Finding important plans and decisions inside noisy group chat.

A mobile-first group chat built around a rule-based scoring and categorization engine. Socket.IO carries live messages while SQLite persists groups, reactions, replies, presence, and the context needed to build Catch Up and Important views.

Normalizes slang, typos, abbreviations, and related phrases before scoring.
Includes matched-rule explanations, regression tests, and deterministic simulations for evaluation.
Separates the social chat experience from an internal audit interface for tuning the classifier.

Node.js · Express · Socket.IO · SQLite · JavaScript · Automated tests

View repository

Data, ML & AIRegression

Housing Price Predictor

Compared linear regression, random forest, and XGBoost on the Ames housing dataset. The pipeline handles missing values by meaning, engineers size and quality interactions, and tunes XGBoost with cross-validation.

Python · pandas · scikit-learn · XGBoost · Jupyter

View repository

Held-out model comparison · R²

Linear regression

0.87

Random forest

≈0.87

Tuned XGBoost

0.9167

Repository-reported result. Kaggle first submission: 0.14146 RMSLE.

Data, ML & AIPipeline

Financial News Pipeline

A scheduled collector parses financial RSS feeds across market categories, deduplicates articles with a database constraint, and stores timestamped headlines in SQLite for analysis and future modeling.

Python · feedparser · SQLite · Scheduling · Data analysis

View repository

COLLECTION PATH / CONTINUOUS

01RSS sourcesmarkets · filings · crypto

02Parsernormalize · timestamp

03SQLitededuplicate · query

04Analysisvolume · velocity · keywords

More work

Project archive

Hardware

Morse Code Transceiver

Calibrated button timing, state-machine decoding, and LED encoding on Arduino.

C++ · Arduino · timing ↗

Systems

Authentication System

Flask auth lifecycle with bcrypt, JWT refresh, role checks, and token revocation.

Flask · SQLAlchemy · JWT ↗

Data / ML

European Football Scoring

Position-aware player scoring and team analysis across major European leagues.

In development

pandas · scikit-learn · Jupyter ↗

Systems

Developer Log API

Layered REST API for work sessions, summaries, streak logic, and peak-hour queries.

Python · Flask · SQLite ↗

Hardware

DHT22 Serial Logger

Sensor-to-CSV pipeline with Arduino sampling and Python time-series plotting.

Arduino · serial · pandas ↗

Systems

GitHub Profile Analyzer

Client-side API aggregation for language, repository, activity, and comparison views.

JavaScript · REST API · CSS ↗

Hardware

Ultrasonic Distance Display

Pulse-timed ranging with an HC-SR04 and proximity states on an I2C display.

C++ · Arduino · I2C ↗

Data + Systems

Spotify Mood Analyzer

OAuth PKCE client that scores listening metadata into explainable mood profiles.

JavaScript · OAuth 2.0 · API ↗

02 / Experience

Working beyond the repo.

Hands-on hardware practice and analytical work that inform how I approach engineering projects.

IEEE · University of Florida

Open Project Space

Hands-on work with soldering, circuit debugging, integrated circuits, Arduino logic, PWM, transistor switching, interrupts, and communication protocols.

The environmental-control capstone combined temperature and light sensing, PWM-driven fan control, transistor switching, display feedback, and microcontroller logic into one hardware–software system.

VDart

Business Analyst Intern

Worked with reporting, workflow automation, and analytics to make business processes easier to inspect and improve. The role strengthened the practical side of translating ambiguous needs into structured systems and useful outputs.

03 / Engineering focus

Computing is a stack.

I chose Computer Engineering because I want to understand that stack from digital logic and processors through embedded firmware and systems software to the data and ML workloads running above them.

Hardware and architecture are the direction I’m pushing deepest. Software and ML remain part of the same picture: they expose the constraints a system must support and make the hardware useful.

Current coursework Digital Logic and Computer Systems · Computer Organization · Data Structures and Algorithms · Linear Algebra for Data Science

Hardware & Architecture

Digital logic, processors, RTL, verification, microcontrollers, and the physical constraints underneath software.

Systems & Software

Firmware, APIs, realtime communication, persistence, security, and the interfaces between components.

Data, ML & AI

Data pipelines, feature engineering, model evaluation, and eventually efficient inference on constrained hardware.

Technical toolkit

Hardware / Embedded: SystemVerilog · C++ · RISC-V RV32I · RTL · Icarus Verilog · ESP32 · Arduino · digital logic · I2C · interrupts · PWM · sensor integration
Systems / Software: Python · JavaScript · Node.js · Express · Flask · REST APIs · Socket.IO · SQLite / SQL · Git
Data / ML: pandas · NumPy · scikit-learn · XGBoost · feature engineering · model evaluation · quantization · embedded inference · Jupyter

04 / Contact

Interested in what I’m building?

I’m looking for engineering internships where hardware, systems, or ML meet real constraints.

erikwoods17@gmail.com

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